1. Field of the Invention
The present invention relates to driver circuits in digital systems for adjusting input impedance and output impedance of respective receivers and transmitters relative to a prescribed impedance of a transmission line.
2. Background Art
Newer processor architecture designs require transfer of data between large integrated circuits at higher speeds. For example, newer PCI bus devices implemented as host bridge devices need to be able to transfer data between a processor bus (i.e., a local bus) and an Input/Output (I/O) bus. For example, newer PCI host bridge devices may utilize HyperTransport™ technology, which specifies a data rate of 1.6 GHz between each differential signal pair. Hence, the newer PCI bus devices need to be implemented using newer semiconductor fabrication process technology to optimize the higher speed requirements of HyperTransport™ technology. Examples of newer semiconductor fabrication process technology involves using thin oxide device technology, where transistors have a device feature size of 0.13 microns, and a gate oxide thickness of 3 nm: such transistors utilize nominal supply voltages of 1.2 volts, and each of the factors of size, supply voltage, and speed must be scalable to provide a faster circuit that has a smaller size and requires less supply voltage.
Newer PCI specifications (e.g., PCI-X) also specify smaller voltage swings for bus signals relative to earlier PCI specifications. Hence, the newer PCI specifications are considered “low-voltage applications” (1.2 to 1.5V), and the earlier PCI specifications are considered “high-voltage applications” due to earlier process technologies utilizing thicker-oxide transistors having, for example, a device constructed to have a feature size of 0.35 microns, and a gate oxide thickness of 7.5 nm and configured for using a 3.3 V nominal supply voltage.
However, the PCI host bridge devices still need to be backwards-compatible with the high-voltage applications. Hence, problems arise in reduced voltage tolerances available due to scaling of process technologies to smaller device sizes, while maintaining voltage levels for the high-voltage applications. In particular, the external voltage swings (e.g., the voltage supply of VDD and VSS) for an integrated circuit) tend to scale lower as the process technologies result in smaller device sizes: as circuits operate faster, the corresponding voltage swing becomes smaller, and the transistors used to build the output drivers also scale to smaller sizes based on the process technology.
The requirements for backwards-compatability requires adding a second group of transistors, distinct from the first group of low-voltage transistors, that can tolerate the larger voltage requirements of the older PCI specifications. The second group of transistors have larger physical dimensions than the first group of low-voltage transistors, and can therefore withstand higher supply voltages. Hence, the thicker gate oxide transistors have a lower switching speed but can withstand a higher supply voltage.
In addition, backwards-compatability requires resolving the combined use of diode structures for Electro Static Discharge (ESD) protection for the first group of transistors with use of the second, larger group of transistors.
In addition, attempts to use thick oxide transistors for the low-voltage applications as well as the high-voltage applications suffers from the disadvantage that it is extremely difficult to obtain sufficient switching speed from the thick oxide transistors to meet the requirements of newer PCI specifications. In particular, the thick oxide transistors are larger structures have a higher capacitance in general, as well as source-drain capacitance; in addition, the higher voltages used in the thick oxide transistors need to transition over a wider voltage range, and the amount of available current to move the voltage through the capacitance is less. Hence, the thick oxide transistors are substantially slower than the thin oxide transistors.
Prior attempts at combining thick oxide transistors and thin oxide transistors on the same silicon substrate have suffered the disadvantage of sacrificing performance in either the high-voltage (low speed) application or the low-voltage (high speed) application; hence, prior attempts have not been able to provide a circuit able to provide optimal performance for both the high-voltage (low speed) application at 3.3V and the low-voltage (high speed) application at 1.5V.